register_16_v1 Project Status
Project File:	simpleCPU.xise	Parser Errors:
Module Name:	register_16_v1	Implementation State:	New
Target Device:	xc3s400-5pq208	Errors:
Product Version:	ISE 14.3	Warnings:
Design Goal:	Balanced	Routing Results:
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:
Environment:		Final Timing Score:

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report
Translation Report
Map Report
Place and Route Report
Power Report
Post-PAR Static Timing Report
Bitgen Report

 

Secondary Reports			[-]
Report Name	Status	Generated

Date Generated: 08/20/2015 - 11:18:31