CONTROL_LOGIC Project Status
Project File: control.xise Parser Errors: No Errors
Module Name: CONTROL_LOGIC Implementation State: Synthesized
Target Device: xc7a100t-3csg324
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
1 Warning (0 new)
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slice LUTs 6 63400 0%
Number of fully used LUT-FF pairs 0 6 0%
Number of bonded IOBs 26 210 12%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentThu Mar 13 21:56:25 202501 Warning (0 new)0
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogCurrentThu Mar 13 22:03:14 2025

Date Generated: 03/15/2025 - 18:17:49