ram Project Status
Project File: memory.xise Parser Errors: No Errors
Module Name: ram Implementation State: New
Target Device: xc7a100t-3csg324
  • Errors:
  
Product Version:ISE 14.7
  • Warnings:
  
Design Goal: Balanced
  • Routing Results:
  
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
  
Environment:  
  • Final Timing Score:
   
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogCurrentWed Mar 12 16:31:33 2025

Date Generated: 03/12/2025 - 16:32:44