computer Project Status (03/13/2025 - 22:16:53) | |||
Project File: | simpleCPU_v1a_vhd.xise | Parser Errors: | No Errors |
Module Name: | computer | Implementation State: | Synthesized |
Target Device: | xc7a100t-3csg324 |
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Product Version: | ISE 14.7 |
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Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Device Utilization Summary (estimated values) | [-] | |||
Logic Utilization | Used | Available | Utilization | |
Number of Slice Registers | 31 | 126800 | 0% | |
Number of Slice LUTs | 73 | 63400 | 0% | |
Number of fully used LUT-FF pairs | 18 | 86 | 20% | |
Number of bonded IOBs | 2 | 210 | 0% | |
Number of Block RAM/FIFO | 1 | 135 | 0% | |
Number of BUFG/BUFGCTRLs | 1 | 32 | 3% |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Wed Mar 12 21:24:28 2025 | ||||
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
CPLD Fitter Report (Text) | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Out of Date | Thu Mar 13 13:02:46 2025 |