LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

use std.textio.all;
use ieee.std_logic_textio.all;

entity bus_monitor is
generic (
  NAME : string := "ACC";
  SIZE : natural := 8 );
port ( 
  A : in std_logic_vector(SIZE-1 downto 0) );
end bus_monitor;

architecture bus_monitor_arch of bus_monitor is
  begin
    process( A )
	   variable L : line;
    begin
      write(L, now);
		write(L, string'(" : "));		
		write(L, NAME);
		write(L, string'(" = "));		
		write(L, A);	
      writeline(output, L);		
    end process;
end bus_monitor_arch;