Games Console

Figure 1: simpleCPU games console

The aim of the simpleCPU teaching processor is that students learn through hands-on experience what a processor is by building one. Therefore, this is a journey from AND-gate to computer, leaving no stone unturned, the incremental refinement of the simpleCPU processor's architecture from version 1a to version 1d. The end goal of this journey being a DIY games console, because as we all know the true reason why computers were invented was to play video games :). Therefore, this web page hopefully pulls together all the existing work into a programming resource, a guide to how to write your own games running on the simpleCPU.

Stuff already made ...

Figure 2: top level block diagram

To state the obvious to create a video games console we need a controller to capture the users inputs / commands, a processor to process these inputs, perform the games logic and create the output graphics, that will be displayed to the user. Fortunately, a number of these key hardware and software components have already been implemented:

Controllers : the first hard requirement of any games console is that the user must be able to interact with the game. This human computer interface can take many different forms, from serial ports allowing the FPGA board to share the PC's keyboard and mouse, or specific hardware connected directly to the FPGA e.g. switches, buttons, joysticks etc :

Game Controllers: to play a game you need a game controller e.g. UART, rotary encoders and Game pads (Link).
Keyboard: the current FPGA board has a PS2 interface, the hope is to use an USB-to-PS2 converter to connect a keyboard to the games console, allowing the user to use the classic WASD keys (WORK IN PROGRESS).

Processor : the processor used in the games console is the simpleCPU_v1d. This is the final processor students use in the module i teach, so is the obvious choice. There are a lot of resources on this processor on the main web page:

SimpleCPU version 1d - fpga: an improved simpleCPU, more memory, more instructions, more addressing modes (Link).
SimpleCPU version 1d - datasheet: a quick reference guide on its architecture and instruction set (Link).
Systems and Devices 1 (SYS1): a lecture series from AND gate to VHDL, discussing the evolution of the simpleCPU processor from version 1a to version 1d (Link).

Display : the second hard requirement of any games console is that the user must be able to see the game. A number of different displays can be connected to the FPGA board, from a serial terminal, LCD displays, to VGA monitors. However, the better the display the more hardware you need and the more complex the design i.e. in many respects the VGA controller used in this games console is more complex that the processor :)

SimpleCPU version 1d - pong: the beginning, turning the SimpleCPU into a games console using ANSI escape sequence graphics across a serial port (Link).
SimpleCPU version 1d - space invaders: finally, getting closer to building a games console, this is the original base system used in this games console: processor + controller + VGA (Link).
LCD display: the FPGA board used in version 1 of the games console comes with a 16X2 LCD display. This display is the same as that used in the original bread-boarded version of the simpleCPU_v1a. This could be used to implement a very simple LCD based game, but perhaps more useful as a means of displaying messages to the user (WORK IN PROGRESS).

SimpleCPU version 1a - bread boarded: simpleCPU v1a implemented on bread board with LCD display (Link).

Console - Version 1.0

Hardware

Figure 3: games console - version 1.0

The first version of the simpleCPU games console (Video) uses an old Xilinx spartan 3E development board. For more technical details on this board: (Link) and for more information about the FGPA used: (Link). The two main reasons why i selected this board were that it has a built in VGA interface (just the connector and resistor based DAC) and we had a big box full of them spare (from an old module we no longer teach). Free is good :). The game consoles case is made from laser cut 3mm acrylic sheet, as shown in figure 4. The DXF files can be downloaded here: (Link). Note, at this time some of the push buttons on the FPGA board are not accessible. It is intended that push rods / buttons will be 3D printed later.

Figure 4: top and bottom panels

The simpleCPU logo and SNES connector box were 3D printed. Note, the logo was generated from a 2D image, imported into Inkscape, then using the Path -> Trace Bitmap tool, the bitmap image is converted into a vector image, that can then be saved as an "AutoCAD DXF R12" file. This DXF file can then be imported into openSCAD using the following commands and combined with other 3D elements. The DXF,SCAD and STL files can be downloaded here: (Link).

$fn=100;
hull(){
    translate([5,20,0]) cylinder(h=2, r=40/2);
    translate([55,20,0]) cylinder(h=2, r=40/2);
}
color("red") scale([2,2,1.25]) translate([-12,-39.5,0]) linear_extrude(height = 4) import("drawing-1a.dxf");

Figure 5: logo

The SNES controller plugs into a 3D printed box, well its hot glued into a 3D printed box, as the SNES socket is proprietary, a Nintendo specific connector which can not be easily obtained. Therefore, electrical connection to these pins are made using solid copper wires, cut to size such that they form a friction fit. These "plug pins" are then soldered to seven-strand copper wire, which in turn plugs into an IO header on the FPGA board. Discussion of the SNES interface controller running in the FPGA can be found here: (Link). The SCAD file can be downloaded here: (Link).

Figure 6: SNES controller box

Electronics

Figure 7: top level architecture

The initial architecture used by this version of the games console is the same as that used in the space invaders demo (Link), shown in figure 7. I decided for the moment to keep the processor's clock speed at 10MHz to ensure stability. However, the synthesis tools do indicate that this design can run a lot faster, as shown in figure 8. Therefore, the system clock in later versions of the games console will be increased to 25MHz - 50MHz.

Figure 8: synthesis report

The core peripheral devices in this version of the games console are an: UART, GPIO, Rotary encoder, SNES and VGA. The memory map used in this architecture is shown in figure 9.

ADDR      A1 A0 CS       WR                        RD

0xFFF     1  1  0        UART_TX                   UART_RX
0xFFE     1  0  0        UART_TX                   UART_STATUS

0xFFD     0  1  1        GPIO A out                GPIO A out          
0xFFC     0  0  1        GPIO A out                GPIO A in 

0xFFB     0  1  2        NU                        NU
0xFFA     1  0  2        ROTARY_RESET              ROTARY_DATA
0xFF9     0  1  3        SNES_DATA                 NU
0xFF8     0  0  3        SNES_START                SNES_STATUS

0xFF7     1  1  6        VGA                       VGA
0xFF6     1  0  6        VGA TILE_Y_REG
0xFF5     0  1  6        VGA TILE_X_REG
0xFF4     0  0  6        VGA CPU_DST_ADDR_REG
0xFF3     1  1  6        VGA CPU_COLOUR_REG        VGA TILE_POS
0xFF2     1  0  6        VGA CPU_DATA_IN_REG       VGA CPU_DATA_OUT_REG
0xFF1     0  1  6        VGA CPU_SRC_ADDR_REG
0xFF0     0  0  6        VGA CPU_CTL_REG           VGA CPU_STATUS_REG 

0xFEF     1  1  MEM      RAM                       RAM
...                      ...                       ...
0x000     0  0  MEM      RAM                       RAM

Figure 9: top level architecture

The bit-file for this system can be downloaded here (Link), this file can be used to configure the FPGA board and will display the test image shown in figure 10.

Figure 10: test image

To upload a new program onto the games console the data2mem command line tool can be used to update the computer.bit bit-file. This program updates the contents of the blockram components on the FGPA i.e. the memory devices used to implement the simpleCPU_v1d's memory, shown in figure 11. Note, just for information, designs that are uploaded onto the FPGA are constructed from a number of fundamental building blocks:

Slices : logic and flip-flops, the small blue squares in the middle section of figure 11.
BlockRam : hardcore memory blocks i.e. memory within the FPGA constructed from dedicated silicon, rather than being constructed from slices. The outer, left hand, larger orange rectangular blocks shown in figure 11 implement the processor's memory. The other larger blue rectangular blocks are blockrams used to implement the VGA video display controllers frame buffer.
Multipliers : hardcore multiplier blocks i.e. multipliers within the FPGA constructed from dedicated silicon, rather than being constructed from slices. The outer, right hand, larger blue rectangular blocks shown in figure 11. Note, the processor has been updated to include a multiply machine level instruction i.e. the ALU contains a multiplier hardware component.

Figure 11: CPU memory

Software

The software tools used to assemble game code can be downloaded here: (Link). To assemble the game code the "makefile" go.sh is used. This script uses the m4 pre-processor to implement macro functionality and an assembler and linker is written in python. Note, the sed command used to remove blank lines did not work in Windows for some reason, not sure why. However, the same functionality can be implemented by replacing this command with grep "\S", which works fine under windows.

#!/bin/sh

# m4 simpleCPUv1d.m4  lcd_test.asm | sed '/^ *$/d' > pass1.asm
# m4 simpleCPUv1d.m4  serialTest.asm | sed '/^ *$/d' > pass1.asm

# m4 simpleCPUv1d.m4  basicTest_1.asm | sed '/^ *$/d' > pass1.asm
# m4 simpleCPUv1d.m4  basicTest_2.asm | sed '/^ *$/d' > pass1.asm
# m4 simpleCPUv1d.m4  basicTest_3.asm | sed '/^ *$/d' > pass1.asm
# m4 simpleCPUv1d.m4  basicTest_4.asm | sed '/^ *$/d' > pass1.asm
# m4 simpleCPUv1d.m4  basicTest_5.asm | sed '/^ *$/d' > pass1.asm

 m4 simpleCPUv1d.m4  basicTest_5a.asm | sed '/^ *$/d' > pass1.asm

# m4 simpleCPUv1d.m4  basicTest_6.asm | sed '/^ *$/d' > pass1.asm
# m4 simpleCPUv1d.m4  basicTest_7.asm | sed '/^ *$/d' > pass1.asm

# m4 simpleCPUv1d.m4  vgaDefault.asm | sed '/^ *$/d' > pass1.asm
# m4 simpleCPUv1d.m4  vgaOXO.asm | sed '/^ *$/d' > pass1.asm
# m4 simpleCPUv1d.m4  vgaSpaceInvaders.asm | sed '/^ *$/d' > pass1.asm
# m4 simpleCPUv1d.m4  vgaGameOfLife.asm | sed '/^ *$/d' > pass1.asm
# m4 simpleCPUv1d.m4  vgaPong.asm | sed '/^ *$/d' > pass1.asm

python3 simpleCPUv1d_as.py -p1 -i pass1 -o pass1
cp tmp.asm tmp1.asm

m4 simpleCPUv1d.m4 tmp.asm | sed '/^ *$/d' > pass2.asm

python3 simpleCPUv1d_as.py -p2 -i pass2 -o code
python3 simpleCPUv1d_ld.py -i code

Figure 12: "makefile" go.sh

The m4 macro declarations are store in the file simpleCPUv1d.m4, for more information how to use the m4 pre-processor, refer here: (Link). The assembly code produced by the m4 pre-processor is then assembled into machine code using the python assembler. The command line parameters supported by the assembler are shown below:

Usage: simpleCPUv1d_as.py -i input_file.asm 
                          -o output_file
                          -a address_offset
                          -p number_of_passes
                          -b byte_addressable
                          -d debug_level

Parameters are passed to the assembler using these command line switches:

-i : assembly language file to be assembled. The .asm file extension may be left off e.g. test.asm and test will both access the file test.asm.
-o : object file filename. Object files produced by the assembler will use this base name e.g. -o code, will produce the object files code.asc, code.dat, code.mem etc. These file formats are described later.
-a : program starting address e.g. -a 123, will allocate the first instruction to address 123. Default starting address is 0.
-p : this assembler is a two-pass assembler i.e. the assembler reads the assembler file twice. First pass will perform basic syntax checking and replace labels with their associated memory addresses. Results stored to tmp.asm. The second pass uses tmp.asm to generate the machine code object files. If this parameter is set to 1 the first pass is performed, if set to 2 the second pass is performed. Default, both passes performed.
-b : use byte addressable memory, no additional parameters passed. Default, word addressable memory used.

-d : debug level, this can be set to 0, 1, or 2. The higher this level the more debugging information regarding the assembler’s operation is outputted to the screen. Default is 0 i.e. minimum information.

To manually assemble a program e.g. test.asm, at the command prompt enter :

python3 simpleCPUv1a_as.py -i test -o code

This will generate the following output files:

tmp.asm : temporary assembly code file, comments and additional white spaces removed. Labels replaced with their numerical values.
code.asc : ASCII hex file for EPROM programmer. Not used.
code.dat : plain text file, instruction address (decimal) followed by machine code ( binary). Useful for debugging.
code.mem : plain text file, instruction address (hex) followed by machine code (hex) reversed nibble format i.e. most significant nibble first. Used by linker to generate memory image file, or to update a bit-file.

To allocate this machine code to specific blocks of memory a linker is used. In general a linker takes one or more assembled object files and libraries to produce a final executable program. As we are using a very simple assembler, this linker could be more accurately referred to as a loader, converting the machine code generated by the assembler into a format that can be loaded into memory (binary image). To generate this binary file, at the command prompt enter :

python simpleCPUv1a_ld.py -i code

The linker reads the object file: code.mem, producing the VHDL file memory.vhd that will be used during the synthesis process to initialise the computer's memory. However, as the hardware comments in this games console will not change, we do not need to re-synthesize the design to update the processors memory. Therefore, the build process when writing software is to first uncomment one of the initial m4 commands in the go.sh script e.g. in figure 12 the example program basicTest_5a.asm. Then at the commandline run the go.sh and update_bit_file.sh scripts, as shown in figure 13.

Figure 13: generating new bit-file.

This will generate the bit-file: new_computer.bit that can be used to configure the games console. To upload this bit-file to the FGPA you will need to run Xilinx Impact upload program. This comes with the Xilinx ISE 14.7 software: (Link). Launch Impact from the command line or start menu, then follow the steps shown in figure 14.

Launch Impact, there will be a series of pop up windows asking if you wish to load an existing design etc, click NO and CANCEL until you get to the start screen shown, then double click on boundary scan.
Right click on centre panel (follow the instructions on screen).
In the pop up menu select initialise chain.
Connected JTAG ICs will then be detected i.e. for the board used in this version of the games console that will be: FPGA, FLASH and CPLD. Click YES to continue.
Browse to the directory containing the update_bit_file.sh script, selecting the new_computer.bit file, click OPEN.
Click NO.
Click BYPASS.
Click BYPASS.
Click OK.
Right click on the green FPGA icon xc3s500e i.e. from the detected JTAG ICs, selecting PROGRAM.
The message PROGRAM SUCCEEDED will be display if the FPGA has been configured correctly, the game will start i.e. you will see the welcome screen etc on the display.

Figure 14: impact

Software

To understand how to program this version of the games controller i have created a series of video tutorials. These talk through how to use the VGA controller (Link) and the other peripheral devices (Link).

This video introduces the background to the games console and hardware used to implement it.

Figure 15: SimpleCPU Games Console : An Overview (Link)

The first peripheral device considered is the video display controller (VDC). In this video the following example code is discussed:

Read single pixel value from the frame buffer: (basicTest_1.asm)
Read multiple pixel values from the frame buffer: (basicTest_2.asm)
Write single pixel value to the frame buffer: (basicTest_3.asm)
Write multiple pixel values to the frame buffer: (basicTest_4.asm)

Figure 16: SimpleCPU Games Console : VDC frame buffer read / write (Link)

To simplify the drawing of "blocky" graphics the VDC support block write and block copy functions, simplifying the process of writing data to the frame buffer. In this video the following example code is discussed:

Block write & copy, Draw box and rectangle: (basicTest_5.asm)

Figure 17: SimpleCPU Games Console : VDC block write / copy (Link)

To show how the Block write and copy commands can be used to implement a simple game, we consider a bouncing ball "game". In this video the following example code is discussed:

Simple bouncing ball code: (basicTest_5a.asm)

Figure 18: SimpleCPU Games Console : Game 1 (Link)

The core graphical construct used in the VDC is the tile, a library of 128, 8x8 graphical elements defined in video memory. In this video the following example code is discussed: